This invention relates to a semiconductor chip carrier structure for testing of the chip prior to the chip being incorporated onto a printed circuit wiring board. The invention is particularly useful in the electrical testing of semiconductor devices packaged in fine pitch carriers where the separation of the electrical contacts to the conductors of the chip are very close together and where the electrical conductors are very narrow.
State of the art packaging of integrated circuits has encouraged the use of chip carrier packages having a large number of input/output (I/O) pads (148 or greater) on a fine pitch (25 to 10 mils) to house monolithic/hybrid die circuits. In the prior art, the socket systems used for test and equipment applications have not kept pace with the density achievable with package evolution. The fine pitch high I/O package has made more difficult the ability to align socket contacts for electrical contact to the I/O pads of the chip carrier packages. In addition, ship board device testing application environments challenges the ability of the socket contacts to maintain electrical connection. Also, because of the fine pitch and high quanity of I/O pads, device to socket alignment can be time-consuming. This significantly adds cost and time to testing and maintennance. It is therefore an object of this invention to provide a socket structure which provides fine pitch electrical contact alignment, integrity of the alignment for test and ship board applications, and importantly, to afford an expedient method of contact alignment that is repeatable.